Metal-oxide-semiconductor field-effect-transistor (MOSFET) scaling continues to be the trend for high-density, high-performance and low-power complementary metal-oxide-semiconductor (CMOS) technology. By employing silicon-on-insulator (SOI) substrates, many concerns and obstacles of low power-supply voltage bulk-silicon CMOS technology can be eliminated (e.g., due to the low power consumption, low leakage current, low capacitance diode structures, etc., of CMOS-on-SOI devices).
Accompanying the growing interest in CMOS-on-SOI is an interest in electrostatic discharge (ESD) protection for CMOS-on-SOI technology. Such interest will peak as the migration from bulk CMOS to CMOS-on-SOI becomes a reality and achieving industry-acceptable ESD results becomes mandatory.
The extension of known ESD circuits from bulk technology to SOI technology has been proposed including SOI-based floating body/grounded gate MOSFET networks, grounded body/grounded gate MOSFET networks, lateral bipolar elements, gated diode structures and the like. Additionally, U.S. Pat. No. 5,811,857, which is hereby incorporated by reference herein in its entirety, discloses a novel body-coupled gated diode for SOI technology that provides superior ESD protection to conventional ESD diodes.
A need nonetheless remains for compact and flexible designs for such SOI-based ESD structures.